This invention relates to terminators which are applicable to metal oxide semiconductor on insulator (MOS-soi) with triple wells integrated circuit technology and which are particularly useful for terminator networks.
This related application(s) and the present application are owned by one and the same assignee, International Business Machines Corporation of Armonk, N.Y.
The descriptions set forth in these co-pending applications are hereby incorporated into the present application by this reference.
Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
For signal interfaces between devices terminators have been used, as described for instance in U.S. Pat. No. 4,748,426: entitled xe2x80x9cActive termination circuit for computer interface usexe2x80x9d, granted May 31, 1988 to Alexander Stewart for Rodime PLC, in an active termination circuit for a computer interface for reducing line reflection of logic signals. Such terminators have used a first and second resistor combination to permanently connect to a signal line that couples a plurality of peripheral devices to one another. The other ends of the first and second resistors are connected through a switching device to a positive voltage supply line and to logic ground, respectively. When termination of multiple devices was required, a plurality of resistor combinations were provided but on/off control of the switch in this example was achieved by one control that is located remote from the termination circuit systems. Integrated circuit interconnection structures have also used precision terminating resistors, as illustrated by U.S. Pat. No. 4,228,369, granted in October, 1980 to Anantha et al. for IBM.
As will be illustrated for chip interconnection, when resistor terminators are used in thin film semiconductor integrated circuits such as those used in metal oxide semiconductors (e.g. CMOS) today, they create hot spots which cannot be adequately cooled, so such resistor terminator circuits which create hot spots cannot be used in metal oxide semiconductor applications to provide terminators for chip to chip connections on chips using IBM""s new sub-micron MOS (CMOS) technologies where because of the high currents used in these networks it is difficult or impossible to meet all the cooling and reliability requirements required for commercial performance. It has become necessary to invent a solution to interfacing devices which can be used in such environments on chips, and used for terminators in networks of chips and devices where there is a need to transmit digital data therebetween without overshoot and undershoot in signal transmission between the chips and devices or systems. These connections need to operate at a faster speed, accommodating data rate speeds ranging into hundreds of Mhz and Ghz.
The creation of a terminator which particularly may be fabricated for high speed metal oxide semiconductor on insulator (MOS-soi) applications with triple wells in integrated circuits is needed.
If, as I have shown in this and other applications, a desired fast data transmission terminator network can be created, as is useful for digital data, eliminating or reducing overshoot or undershoot in signal transmission between chips and between systems, it would be even more desirable to have additional uses for the terminator, and I have discovered how this can be done.
This invention relates to CMOS-SOI fabricated terminator network making a CMOS small signal switchable adjustable impedance terminator network possible which is not useful for fast transmission of digital data, eliminating or reducing overshoot and undershoot in signal transmission between chips and between systems, in serial links and data buses, for minimizing ringing and similar noise problems, for providing electrostatic discharge (ESD) protection, particularly in high speed metal oxide semiconductor (MOS) integrated circuit applications, and mixed vender technology interface communications, but also one which can operate in different packages as well as in system tuning for perfect termination. The CMOS terminator circuit includes a terminator inhibit control input circuit coupled to the terminator reference circuit and its input circuit to enable and disable the terminator network with a switching control signal. One or more terminal circuit adjustment sections enable one or more levels of impedance adjustment.
The demand for fast data transmission has pushed the data rate into hundreds of Mhz and Ghz. Therefore it is advantages to reduce the signal swing so that the signal reach its desired digital ones or zeros voltage levels faster with lower power and with less noise generation.
With the terminator inhibit control input circuit and one or more terminal circuit adjustment sections for multiple levels of impedance adjustment the terminator circuit which is useful for high speed transmission and interoperability between chips and systems can be even more useful by providing a way to be able to control and adjust the impedance of the terminator so that it can operate the part in different packages as well as in system tuning for perfect termination. This will allow a part to have multiple usage. This can be a much needed cost saving chips part number reduction or a high volume ASIC OEM useful circuit.
The present invention is able to switch into high impedance so that the driver can take control of the line and drive out for the bi-directional data buses that are used in all computer systems today.
The circuit is able to turnoff all currents to support the CMOS leakage test so that chips with defects can be found quickly and easily. The circuit is able to adjust impedance of the terminator so that this circuit can have multiple usage.
Furthermore, the circuit is able to fine tune the terminator to have the desired reflection for the nets. This helps to overcome any process tolerances.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.